1. Field of the Invention
The present invention relates generally to dynamic type semiconductor memory devices, particularly to a semiconductor memory device having a shared sense amplifier arrangement wherein one sense amplifier is shared between the columns in two different memory blocks. More specifically, the present invention relates to circuit for generating a control signal to connect shared sense amplifiers to the corresponding columns,
2. Description of the Background Art
In a dynamic type semiconductor memory device (DRAM), information is stored in the form of electric charges in a capacitor. In reading data, the signal charges stored in the capacitor are transferred onto a bit line (data line). A small change in potential is produced on the bit line depending on the existence of the signal charges transferred onto the bit line, and the potential change is sensed and amplified by a differential operation type sense amplifier to read the information.
As a semiconductor memory device is highly integrated to reduce the size of a memory cell, the inevitable is a tendency of reduction in storage capacitance of a memory capacitor. Various improvements have been made for obtaining sufficient difference in input potentials (signal voltage) for a sense amplifier against the reduced size of the memory cell followed by the reduced storage capacitance.
One of such conventional countermeasures is U.S. Pat. No. 4, 351,034 issued Sep. 21, 1982, entitled "Folded Bit Line-Shared Sense Amplifier" by S. S. Eaton et al. and assigned to Inmos Corporation. This U.S. patent employs the shared sense amplifier arrangement wherein a memory cell array is divided into two blocks and sense amplifiers are disposed and shared between the two blocks. During the sensing operation, only the columns in one block are connected to the sense amplifiers and the columns of the other block are subsequently connected to the sense amplifiers after the sensing operation.
With the above-described arrangement, since the number of memory cells connected to one bit line can be reduced, parasitic capacitance of a bit line associated with the memory cells is reduced, so that even if the same amount of signal charges are transferred onto the bit line, potential change on the bit line can be almost twice that in a non-divided cell array. This is possible because the potential on the bit line varies in proportion to a ratio Cs/Cb of a memory cell capacitance Cs to a bit line capacitance Cb.
The development of the above-described shared sense amplifier arrangement is a multi-divisional bit line arrangement as disclosed in Japanese Patent Laying Open No. 57-100689. In the multi-divisional bit line arrangement, a memory cell array is divided into four or more blocks and the number of sense amplifiers is increased in order to reduce the number of memory cells connected to one bit line. In this case, one sense amplifier is shared between two bit line pairs included in different memory cell blocks. It is structured such that in the operation, while a cell block including selected memory cells is connected to sense amplifiers to be subjected to sensing operation, sense amplifiers connected to memory cell arrays without the selected memory cells is not activated to be placed in a standby state. This arrangement enables not only the enhancement in a read signal voltage from a memory cell but also the reduction of power consumption associated with charge/discharge of bit lines during the operation of the sense amplifiers because the sense amplifiers are selectively activated. Therefore this arrangement will be widely and in large capacity DRAMs of 4 megabits and 16 megabits.
FIG. 1 is a diagram showing an arrangement of a modified conventional DRAM chip employing the multi-divisional bit line arrangement. FIG. 1 shows an example of an arrangement of 256 KW (kilo word) by one bit. Referring to FIG. 1, a semiconductor chip 100 comprises an address input terminal 52 for receiving a row address RA0-RA8 and a column address CA0-CA8 applied in a time-division multiplexing manner, an input terminal 51 for receiving a row address strobe signal RAS for supplying timing of strobing the row address applied in the time-division multiplexing manner into the device, an input terminal 53 for receiving a column address strobe signal CAS for supplying timing of strobing the column address into the device, an input terminal 54 for receiving a read/write control signal R/W for defining reading/writing operations of the memory device, a data input terminal 55 for receiving input data D.sub.IN, and a data output terminal 56 for supplying output data D.sub.OUT. The semiconductor chip 100 is further provided with a terminal for supplying a power supply voltage Vcc which becomes a reference voltage and a terminal for supplying a ground potential Vss, though they are not shown.
In FIG. 1, the semiconductor memory device includes a memory cell array divided into four memory blocks 1a, 1b, 1c and 1d each having one or more rows of memory cells and sense amplifier bands 2a and 2b shared between two blocks. The sense amplifier band 2a is shared between the memory cell blocks 1a and 1b and the sense amplifier band 2b is shared between the memory cell blocks 1c and 1d. The sense amplifier bands 2a and 2b include sense amplifiers provided corresponding to the respective columns (bit line pairs) of the corresponding block for differentially amplifying signal potentials on the corresponding columns in response to control signals SFU, SU, SU and SFL, SL and SL, respectively.
Row decoders 3, word drivers 4, a row address buffer 5, a row predecoder 13, a .phi.x (word line drive master signal) generating circuit 7 and a .phi.x subdecoder 12 are provided for selecting one row (one word line) of the memory cell array in response to external address signals. The row address buffer 5 receives 9-bit address signals A0-A8 applied to the address input terminals 52 and generates complementary internal row address signals RA0, RA0-RA8 and RA8 in response to internal control signals from a RAS buffer 6.
The row predecoder 13 decodes the internal row address signals RA2, RA2-RA7 and RA7 from the row address buffer circuit 5 and generates a total of 12 predecoded signals X1-X4 (generically represented as Xi), X5-X8 (generically represented as Xj) and X9-X12 (generically represented as Xk). While the correspondence of the predecoded signals X1-X12 to the memory cell blocks is arbitrary, for the purpose of the simplicity of description, it is assumed in the following that the predecoded signals Xi (X1-X4) are used as signals for designating memory cell blocks.
FIG. 2 schematically shows arrangements of the address buffer 5 for generating the internal row address signals RA2 and RA3, and RA2 and RA3 from the external address signals A2 and A3 and the row predecoder 13 for generating the predecoded signals Xi. In FIG. 2, the row address buffer 5 includes a buffer circuit 5a for generating the internal row address signals RA2 and RA2 complementary with each other in response to the external address signal A2 and a buffer circuit 5b for generating the internal row address signals RA3 and RA3 complementary with each other in response to the external address signal A3.
The row predecoder 13 includes a decoder circuit 13a for generating the predecoded signal X1 in response to the internal row address signals RA2 and RA3, a decoder circuit 13b for generating the predecoded signal X2 in response to the internal row address signals RA3, a decoder circuit 13c for generating the predecoded signal X3 in response to the internal row address signals RA2 and RA3, and a decoder circuit 13d for generating the predecoded signal X4 in response to the internal row address signals RA2 and RA3. Each of the predecoder circuits 13a to 13d has the same circuit arrangement. When the predecoded signals X1 to X4 are used as block designating signals, only one of the predecoded signals X1 to X4 enters a selected state to be, for example, a "H" (logical high) level. Each of the predecoder circuits 13a to 13d is comprised of an AND gate or NAND gate. The circuits for generating the other predecoded signals Xj and Xk have the same arrangement.
Back to FIG. 1, the .phi.X generating circuit 7 generates a word line drive master signal .phi.x for driving a word line in response to the internal clock signals from the RAS buffer 6 and applies the same to the .phi.x subdecoder 12. The .phi.x subdecoder 12 generates word line sub-decoded signals .phi.X1-.phi.X4 in response to the internal row address signals RA0, RA0, RA1 and RA1 and the word line driving signal .phi.x from the row address buffer 5 to generate word line sub-decoded signals .phi.x1 to .phi.x4 and applies the same to the word driver 4. Only one of the word line sub-decoded signals .phi.x1-.phi.x4 rises to the "H" level.
FIG. 3 is a schematic diagram of an arrangement of the .phi.x subdecoder. In FIG. 3, .phi.x subdecoder 12 includes subdecoding circuit 12a-12d. The subdecoding circuit 12a selectively passes the word line driving master signal .phi.x in response to the internal row address signals RA0 and RA1 to generate the word line sub-decoded signal .phi.xl. The subdecoding circuit 12b selectively passes the word line driving master signal .phi.x in response to the internal row address signals RA0 and RA1 to generate the word line sub-decoded signal .phi.x2. The subdecoding circuit 12c selectively passes the word line driving master signal .phi.x in response to the internal row address signals RA0 and RA1 to generate the word line sub-decoded signal .phi.x3. The subdecoding circuit 12d selectively passes the word line driving master signal .phi.x in response to the internal row address signals RA0 and RA1 to generate the word line sub-decoded signal .phi.x4.
Back to FIG. 1, the row decoder 3 further decodes the predecoded signals Xi, Xj and Xk from the row predecoder 13 to generate decoded signals for selecting four word lines. The word driver 4 transmits the word line driving signal onto one word line in response to the decoded signals from the row decoder 3 and the word line subdecoded signal .phi.x1-.phi.x4 from the .phi.x sub-decoder 12. FIG. 4 shows one example of a specific arrangement of the row decoder 3 and the word driver 4.
FIG. 4 shows a unit row decoder and an associated word driver as representatives. Referring to FIG. 4, a unit row decoder 30 includes a 3-input AND circuit for receiving 3-bit predecoded signals Xi, Xj and Xk and an inverter for inverting an output of the NAND circuit.
The NAND circuit includes a p channel insulated gate type field effect transistor (referred to as p MIS transistor hereinafter) PT1 and an n channel insulated gate type field effect transistor (referred to as n MIS transistor hereinafter) NT1 each having a gate for receiving the predecoded signal Xi, an n MIS transistor NT2 with a gate for receiving the predecoded signal Xj, an n MIS transistor NT3 with a gate for receiving the predecoded signal Xk and a p MIS transistor PT2 with a gate for receiving inverter output. The p MIS transistors PT1 and PT2 are provided in parallel with each other between a power supply voltage Vcc and a node N1. The n MIS transistors NT1, NT2 and NT3 are connected in series between the node N1 and a ground potential Vss.
The inverter includes a p MIS transistor PT3 and an n MIS transistor NT4 each having a gate for receiving an output of the NAND circuit. The p MIS transistor PT3 and the n MIS transistor NT4 are complementarily connected between the power supply potential Vcc and the ground potential Vss. The unit row decoder 30 outputs the output of the NAND circuit (potential at the node N1) and an output of the inverter (potential at a node N2), which are transmitted to four word driving circuits.
Four word driving circuits 4a, 4b, 4c and 4d are provided for one unit row decoder 30. The word driving circuit 4a includes an n MIS transistor NT5 for transmitting the potential of the node N2 of the unit row decoder 30, an n MIS transistor NT6 having a gate for receiving the transmitted potential from n MIS transistor NT5 to selectively transmit the word line sub-decoded signal .phi.x1 onto a word line WL1 and an n MIS transistor NT7 having a gate for receiving the potential at the node N1 of the unit row decoder 30 to selectively connect the word line WL1 to the ground potential. The transistor NT5 acts as a decoupling transistor for decoupling the gate of the transistor NT6 from the node N2.
While each of the word driving circuits 4b, 4c and 4d has the same circuit arrangement as that of the word driving circuit 4a, it differs from the circuit 4a in a name of the transmitted word line sub-decoded signal. More specifically, the word driving circuit 4b selectively transmits the word line sub-decoded signal .phi.x2 onto a word line WL2 in response to the output of the unit row decoder 30. The word driving circuit 4c selectively transmits the word line sub-decoded signal .phi.x3 onto a word line WL3 in response to the output of the unit row decoder 30. The word driving circuit 4d selectively transmits the word line sub-decoded signal .phi.x4 onto a word line WL4 in response to the output of the unit row decoder 30.
In the unit row decoder 30, only when all the predecoded signals Xi, Xj and Xk are at the "H" level, the potential of the node N1 attains an "L" (a logical low) level and correspondingly the potential of the node N2 attains the "H" level. When the potential of the node N2 is at the "H", the n MIS transistor NT6 receives a signal of the "H" at its gate through the n MIS transistor NT5 and becomes conductive in each of the word driving circuits 4a, 4b, 4c and 4d. As a result, the word line sub-decoded signal .phi.x1-.phi.x4 are transmitted onto the word lines WL1-WL4, respectively. Only one of the word line sub-decoded signal .phi.x1-x4 rises to the "H" level.
Accordingly, only one of the word lines WL1-WL4 is driven to the "H".
When at least one of the predecoded signals Xi, Xj and Xk is at the "L" level, the potential of the node N1 attains the "H" level (charged through the p MIS transistor PT2) and the potential of the node N2 attains the "L" level, so that the unit row decoder 30 enters a non-selection state.
Back to FIG. 1 again, the semiconductor memory device further comprises a column address buffer 14 for receiving the address signals from the address input terminals 52 to select four columns of the memory cell array and for generating internal column address signals CA0-CA8 and CA0-CA8, a column predecoder 15 for decoding the internal column address signals CA0-CA7 and from the column address buffer 14 to generate 16-bit predecoded signals Y1-Y4 (generically referred to as Yi hereinafter), Y5-Y8 (generically referred to as Yi hereinafter), Y9-Y12 (generically referred to as Yk hereinafter) and Y13-Y16 (generically referred to as Y hereinafter) and a column decoder 16 for generating a column selecting signal CS for selecting four columns in response to the column predecoded signals Yi, Yj, Yk and Yl. In response to an internal control signal generated from a CAS buffer 19 in response to the column address strobe signal CAS, the column address buffer 14 strobes addresses applied to the address input terminals 52 to generate internal column address signals.
The column predecoder 15 has the same arrangement as that of the row predecoder 13 shown in FIG. 2.
FIG. 5 shows one example of the specific arrangement of the column decoder 16.
Referring to FIG. 5, the column decoder 16 comprises p MIS transistors PT10, PT11, PT12 and PT13 connected in parallel with each other between the power supply voltage Vcc and a node N10, n MIS transistors NT10, NT11, NT12 and NT13 connected in series between the node N10 and the ground potential Vss, and an inverter for inverting a potential of the node N10 and transmitting the inverted potential to a node N11. The inverter includes a p MIS transistor PT14 and an n MIS transistor NT14.
Each of the p MIS transistor PT10 and the n MIS transistor NT10 has a gate for receiving the column predecoded signal Yi. Each of the p MIS transistor PT11 and the n MIS transistor NT11 has a gate for receiving the column predecoded signal Yj. Each of the p MIS transistor PT12 and the n MIS transistor NT12 has a gate for receiving the column predecoded signal Yk. Each of the p MIS transistor PT10 and the n MIS transistor NT13 has a gate for receiving the column predecoded signal Yl. A column selecting signal CS is generated from the node N11. In the arrangement of the column decoder shown in FIG. 5, when all the column predecoded signals Yi, Yj, Yk and Yl are at the "H" level, the potential of the node N10 attains the "L", whereby the column selecting signal CS of the "H" is generated.
Back to FIG. 1 again, an I/O decoder 17 for selecting one of the four columns selected by the column decoder 16 is provided. The I/O decoder 17 decodes the internal row address signals RA8 and RA8 from the row address buffer 17 and the internal column address signals CA8 a from the column address buffer 14 and selects a pair of buses among four pairs of buses on I/O bus 40.
A read/write control circuit 18, a read/write buffer 20, an input buffer 21 and an output buffer 22 are provided in order to receive/transfer data between the one pair of buses selected by the I/O decoder 17 and the external devices. In response to a read/write control signal R/W applied through the input terminal 54 and an internal control signal (internal CAS signal) applied from the CAS buffer 19, the read/write buffer 20 generates a timing signal for defining data writing/reading and applies the same to the read/write control circuit 18. The read/write control circuit 18 connects the pair of buses selected by the I/O decoder 17 with the input buffer 21 or the output buffer 22 in-response to the control signal from the read/write buffer 20.
The input buffer 21 receive input data D.sub.IN applied through the input terminal 55 to generate the corresponding internal data (ordinarily, complementary data pair). The output buffer 22 receives the internal data transferred from the read/write control circuit 18, converts the same into the corresponding output data D.sub.OUT and applies the converted data to the output terminal 56.
A shared sense amplifier control signal generating circuit 8 and a sense amplifier control circuit 23 are provided in order to selectively connect the sense amplifier bands 2a and 2b to the memory cell blocks to operate the sense amplifiers included therein. The shared sense amplifier control signal generating circuit 8, in response to the row predecoded signal Xi from the row predecoder 13, generates selective connection control signals (shared sense amplifier control signals) SA, SB, SC and SD for the sense amplifier bands 2a and 2b and the memory blocks 1a-1d. The shared sense amplifier control signal SA controls connection between the sense amplifier band 2a and the memory cell block 1a. The shared sense amplifier control signal SB controls connection between the sense amplifier band 2a and the memory cell block 1b. The shared sense amplifier control signal SC controls connection between the sense amplifier band 2b and the memory cell block 1c. The shared sense amplifier control signal SD controls connection between the sense amplifier band 2b and the memory cell block 1d.
The sense amplifier control circuit 23 generating a control signal for selectively activating the sense amplifiers includes an SF (sense fast) signal generating circuit 9 responsive to the word line driving master signal .phi.x from the .phi.x generating circuit 7 and the predecoded signal Xi from the row predecoder 13, for generating signals SFU (sense fast upper blocks) and SFL (sense fast lower blocks) for activating sense amplifier in either the sense amplifier band 2a or 2b, a first sense amplifier activating signal generating circuit 10 responsive to the control signal from the SF signal generating circuit 9 for generating first sense amplifier activating signals SU and SL, and a second sense amplifier activating signal generating circuit 11 responsive to the activating signals from the first sense amplifier activating signal generating circuit 10 for generating second sense amplifier activating signals SU and SL. The control signal SFU is applied to the sense amplifiers included in the sense amplifier band 2a. The control signal SFL is transmitted to the sense amplifiers included in the sense amplifier band 2b. The first sense amplifier activating signals SU and SL activate the sense amplifiers comprising the n channel MIS transistors, which will be described later in detail. The second sense amplifier activating signals SU and SL activate the sense amplifiers comprising the p channel MIS transistors.
FIG. 6 shows one example of an specific arrangement of the SF signal generating circuit 9. Referring to FIG. 6, the SF signal generating circuit 9 has two circuit portions, a circuit for generating the control signal SFU and a circuit for generating the control signal SFL. Since these circuit portions have the same arrangement, FIG. 6 shows the circuit incorporated into one. Referring to FIG. 6, the SF signal generating circuit 9 includes a Sdelay circuit 60 for delaying the word line driving master signal .phi.x by a predetermined time period, an OR gate 61 receiving the row predecoded signals X1 and X2, and an AND gate 62 receiving outputs of the delay circuit 60 and the OR gate 61. The AND gate 62 generates the control signal SFU. When the OR gate 61 receives the row predecoded signals X3 and X4, the control signal SFL is generated from the AND gate 62.
As clearly seen from FIG. 6, when the block 1a or 1b includes the selected memory cells, the sense amplifiers included in the sense amplifier band 2a are activated. In addition, when the block 1c or 1d includes the selected memory cells, the sense amplifiers included in the sense amplifier band 2b are activated.
FIG. 7 shows one specific example of a circuit arrangement wherein the second sense amplifier activating signal SU (SL) is generated in response to the first sense amplifier activating signal SU (SL). Referring to FIG. 7, the second sense amplifier activating signal generating circuit 11 includes a delay stage for delaying the first sense amplifier activating signal by a predetermined time period and a circuit portion for generating the second activating signal SU (SL) in response to a delay activating signal delay from the delay stage and to the control signal RAS. The delay stage is comprised of even-numbered cascade-connected of CMOS inverters each including p MIS transistor PT20-PT22 and n MIS transistors NT20-NT22.
The circuit portion for generating the second activating signal includes a p MIS transistor PT23 and an n MIS transistor NT23 each having a gate for receiving the delay activating signal Sdelay, a p MIS transistor PT24 connected in parallel with the p MIS transistor PT23 and having a gate for receiving the control signal RAS, and an n MIS transistor NT24 connected in series between the p MIS transistor PT24 and the n MIS transistor NT23 and having a gate for receiving the control signal RAS. The delay activating signal Sdelay is a signal obtained by delaying the activating signal SU (SL) by a predetermined time period. When the control signal RAS is at the "H" and the semiconductor memory device is in an operation state, the p MIS transistor PT24 is in an off state and the n MIS transistor NT24 is in an on state. Accordingly, the signal SU (SL) which is an inversion of the delay activating signal Sdelay is generated from a node N35.
When the control signal RAS is at the "L" and the semiconductor memory device is in a standby state, the p MIS transistor PT24 is in the on state and the n MIS transistor NT24 is in the off state. Accordingly, the control signal SU (SL) attains the "H" level irrespective of a signal potential of a node N34. Note that, since in FIG. 7 the signals SU and SL are generated from the activating signals SU and SL, respectively, in the same circuit arrangement, that for the sense amplifier activating signal SL is shown in parenthesis.
While the arrangement of the first activating signal generating circuit 10 is not shown which generates the first activating signals SU and SL in response to the activating signal SFU (SFL) from the SF signal generating circuit 9, any circuit arrangement for simply buffering the control signal SFL and SFU may be employed.
FIG. 8 shows arrangements of two pairs of bit lines in each of the memory cell blocks 1a and 1b and the related sense amplifier band 2a in detail. The bit lines are of the folded bit line pair arrangement wherein the bit lines BL and BL are provided in pair. A memory cell MC is disposed at a crossing portion between one word line WL and a pair of bit lines. The memory cell MC comprises a memory capacitor C for storing information in the form of electric charges and a memory transistor MT responsive to a signal potential on the word line WL for connecting the memory capacitor to the bit line BL (or BL).
In order to differentially sense and amplify a signal potential on a bit line pair, provided to each bit line pair are a p channel sense amplifier PSA comprising cross coupled p MIS transistors PT40 and PT41, a gate of the former coupled to a drain of the latter and a drain of the former to a gate of the latter, and an n channel sense amplifier NSA comprising cross coupled n MIS transistors NT40 and NT41, a gate of the former coupled to a drain of the latter and a drain of the former to a gate of the latter. In order to activate the p channel sense amplifier PSA, a p MIS transistor PT45 is provided which becomes conductive in response to the second sense amplifier activating signal SU and transmits the power supply potential Vcc to sources of the p MIS transistors PT40 and PT41. In order to activate the n channel sense amplifier NSA, provided are an n MIS transistor NT45 which becomes conductive in response to the control signal SFU and transmits a potential of the ground potential Vss level to sources of the n MIS transistors NT40 and NT41, and an n MIS transistor NT46 which becomes conductive in response to the sense amplifier activating signal SU and similarly transmits the potential of the ground potential Vss level to the sources of the n MIS transistors NT40 and NT41. The signal SFU activates the transistor NT45 of a relatively small size to cause initial precise, but slow, sensing operation. The signal SU activates the transistor NT46 of a relatively large size to cause main rapid sensing operation.
A precharging/equalizing circuit EQ is provided for precharging and equalizing each bit line pair to a predetermined potential V.sub.BL when the semiconductor memory device is in the stand by state (when the signal RAS is at the "H"). The precharging/equalizing circuit EQ comprises an n channel MIS transistor T20 being rendered conductive in response to an equalization instructing signal BLEQ to electrically short-circuit the bit lines BL and BL and n channel MIS transistors T21 and T22 being rendered conductive in response to the equalization instructing signal BLEQ to transmit the predetermined potential V.sub.BL to the bit lines BL and BL.
Bit line selecting switches BSA and BSB are provided to each bit line pair in order to selectively connect the bit line pairs to the sense amplifiers. The selecting switch BSA selectively connects the bit line pair of BL and BL of the memory cell block la to the sense amplifier band 2a in response to a selection control signal SA. The bit line selecting switch BSB selectively connects the bit line pair of BL and BL of the memory cell block lb to the sense amplifier band 2a in response to a connection control signal SB. The selecting switch BSA comprises transfer gates T10 and T11 being turned on in response to the selection control signal SA. The selecting switch BSB includes transfer gates T15 and T16 being rendered conductive in response to the control signal SB.
Provided to each bit line pair is an IO switch IOSW for connecting a pair of bit lines to the I/O bus 40 in response to a column selecting signal CS from the column decoder 16. While four pairs of bit lines are connected to four pairs of buses of the I/O bus 40 in response to the column selecting signal CS, FIG. 8 shows only two pairs of bit lines selected simultaneously as a representative. The I/O switch IOSW includes transfer gates T30 and T31 being rendered conductive in response to the column selecting signal CS. The paired IO switches IOSWs connect four pairs of bit lines to the different I/O bus pairs. Ordinarily, the potential V.sub.BL for precharging and equalizing the bit line pair of BL and BL to a predetermined potential in a stand-by state is set to the power supply potential Vcc or to a potential level one half of the same. Now, an operation thereof will be described with reference to operation waveform diagram shown in FIG. 9, wherein FIG. 9 (f) shows levels of the connection control signals SA-SD of a conventional DRAM and FIG. 9 (g) shows signal levels of the connection control signals SA-SD of the modified conventional DRAM. An operation of the modified conventional DRAM shown in FIG. 9 (g) will be described in the following.
When the control signal RAS is at the "H", the semiconductor memory device is in the stand-by state wherein the bit line pair of BL and BL is maintained at the predetermined potential V.sub.BL by the precharging/equalizing circuit EQ. The connection control signals SA-SD are at a boosted potential level of Vcc+.alpha. higher than the power supply voltage Vcc. Thus, each of the bit line selecting switches BSA and BSB is in the on state, each bit line pair of the memory cell blocks 1a and 1b is connected to the sense amplifiers PSA and NSA and similarly the memory cell blocks 1c and 1b are connected to the sense amplifiers included in the sense amplifier band 2b.
When the control signal RAS falls to the "L", the semiconductor memory device is brought into the operation state. In response to falling of the control signal RAS to the "L", the row address buffer 5 is activated, thereby receiving 9-bit addresses A0-A8 applied to the address input terminals 52 to generate the internal row address signals RA0, RA0-RA8 and RA8. The row predecoder 13 predecodes the predetermined internal address signals RA2, RA2-RA7 and RA7 from the row address buffer 5 to generate the predecoded signals Xi, Xj and Xk. Now, consider a case wherein out of the predecoded signal Xi, the predecoded signal X1 is at the "H" and the other predecoded signals X2, X3 and X4 are at the "L" level and the memory cell block 1a is selected. The row decoder 3 decodes the predecoded signals Xi, Xj and Xk from the predecoder 13. A unit row decoder is selected wherein all of the 3-bit predecoded signals Xi, Xj and Xk are at the "H".
Meanwhile, in response to the control signal RAS changing toward the "L", the .phi.x generating circuit 7 generates the word line driving master signal .phi.x and applies the same to the sense amplifier control circuit 23 and the .phi.x subdecoder 12. The .phi.x subdecoder 12 subdecodes the word line driving master signal .phi.x by the internal address signals RA0, RA1 and from the row address buffer 5 and causes only one of the word line sub-decoded signal .phi.x1-.phi.x4 to rise to the "H" and transmits the same to the word driver 4. The word driver 4 selects one word line in response to the decoded signal from the row decoder 3 and the word line sub-decoded signal from the .phi.x subdecoder 12 and causes a potential thereof to rise to the "H" level. In this example, the word line included in the memory cell block la is selected. When the word line WL is selected and a potential thereof is raised, the memory transistor MT in the memory cell MC is rendered conductive, so that a signal potential stored in the related memory capacitor C is transmitted to the related bit line in each bit line pair, thereby producing a potential difference between bit lines in each bit line pair.
Meanwhile, the shared sense amplifier control signal generating circuit 8 causes the connection control signal SB to the "L" level in response to the predecoded signal Xi from the row predecoder 13 and the signal RAS of the low level (the signal RAS of the high level) is generated from the RAS buffer 6, and is applied to the shared sense amplifier control signal generating circuit 8 to separate the sense amplifier band 2a from the memory cell block 1b. On this occasion, the connection control signals SA, SC and SD still remain at the boosted potential level of Vcc+.alpha..
Consequently, the SF signal generating circuit 9 included in the sense amplifier control circuit 23 generates a signal for activating either the sense amplifier band 2a or the sense amplifier band 2b in response to the word line driving master signal .phi.x from the .phi.x generating circuit 7 and the predecoded signal Xi from the predecoder 13. In the operation waveform diagram shown in FIG. 9, the control signal SFU attains the "H" level and the control signal SFL remains at the "L". In response thereto, the n channel sense amplifiers NSA of the sense amplifier band 2a are activated, whereby the bit line at the lower potential starts being discharged. Subsequently, the first sense amplifier activating signal SU is generated in response to the control signal SFU, and then the second sense amplifier activating signal SU is generated after the lapse of a predetermined delay time period. As a result, both of the n channel sense amplifiers NSA and the p channel sense amplifiers PSA in the sense amplifier band 2a are activated, whereby the bit line at the lower potential is discharged to the ground potential Vss level and the bit line at the higher potential is charged to the power- supply potential Vcc level.
On this occasion, the shared sense amplifier control signal generating circuit 8 lowers the connection control signal SA down to the power supply potential Vcc level in response to the generation of the control signal SFU and after establishing the potential on the bit line pair at the power supply potential Vcc level and the ground potential Vss level, the circuit 8 boosts the connected control signal SA to the voltage level of Vcc+.alpha. higher than the power supply voltage.
While the non-selected cell blocks 1c and 1d are connected to the sense amplifier band 2b, the sense amplifier activating signals SFL, SL and SL remain in the same state as the stand-by state and the sense amplifiers included in the sense amplifier band 2b remain inactive.
As the sensing operation proceeds, the control signal CAS falls to the "L" and the CAS buffer 19 generates internal control signals for activating the operation of the column selecting circuitry. In response thereto, the column address buffer 14 generates the internal column address signals CA0, CA0-CA8, and CA8. The column predecoder 15 predecodes the internal column address signals from the column address buffer 14 to generate the column predecoded signals Yi, Yj, Yk and Yl and applies the same to the column decoder 16. The column decoder 16 selects a unit column decoder in which all the predecoded signals Yi, Yj, Yk and Yl are at the "H" to generate the column selecting signals CS of the "H". In response thereto, 4-bit, that is, four pairs of bit lines are selected and the IO switches IOSW become conductive, whereby the selected 4-bit bit line pairs are connected to the I/O bus 40. One pair among the four pairs of buses in the I/O bus 40 is selected by the I/O decoder 17, which is connected to the read/write control circuit 18. When the control signal from the read/write buffer 20 indicates the reading mode, the data on the I/O bus selected by the I/O decoder 17 is transferred to the output buffer 22 and then it is applied as the output data DOUT to the output terminal 56.
In the writing operation mode of the semiconductor memory device, the writing data is transferred onto the selected I/O bus through the input buffer 21 and then written in the selected memory cells through the same operation as described above.
The above described operation waveform diagram shown in FIG. 9 are disclosed in, for example, Japanese Patent Laying Open No. 60-694. According to the prior art, the selecting switch BS (generically represents the switches BSA, BSB, . . . ) is turned on when the semiconductor memory device is in a stand by state for the purpose of equalizing a precharge potential of each bit line pair and maintaining input nodes of a sense amplifier at the precharge potential.
With the above described arrangement, by rendering a sense amplifier non-operated in response to an address signal (block selection designating signal), charging and discharging currents can be reduced during the sensing operation, thereby reducing power consumption.
In addition, in the prior art, the reasons are as follows why the blocks connected to non-operated sense amplifiers (the sense amplifier band 2b according to the operation waveform diagram shown in FIG. 9) are connected to these sense amplifiers. Namely, interconnection capacitances exist on the signal lines transmitting the shared sense amplifier control signals SA-SD and gate capacitances of the MIS transistors constituting the switch BS also exist. Accordingly, setting the signals SA-SD to the "L" level results in wasteful discharge of the electric charges charging the parasitic capacitance on the signal interconnection line and the gate capacitance of the switch BS, which causes the power consumption of the memory device to increase. In addition, setting the control signals SC and SD to the "L" in order to separate the memory blocks similarly connected to the non-operated sense amplifiers (blocks 1c and 1d in the above described example) from the sense amplifiers results in the increase in the number of signal lines of the ground potential Vss level, which increases the noise due the coupling capacitance and might cause the semiconductor memory device to malfunction.
In addition, the reason why the control signals SA-SD are boosted up to the boosted level Vcc+.alpha. is that when the semiconductor memory device is operated during the fluctuations of the power supply voltage Vcc under a certain condition, a case may occur in which a bit line potential becomes higher than potentials of the control signals SA-SD, so that the switch BS which has to remain conductive becomes non-conductive, whereby no information of the memory cells might be transmitted to the input nodes of the sense amplifiers. In the prior art, the precharge potential of the bit line is set to the power supply potential Vcc level (to be exact, Vcc-Vth level). Here, Vth is a threshold voltage of the transfer gate included in the precharging/equalizing circuit. In such a case of power supply voltage fluctuations, the memory device may malfunction. The control signals SA-SD are set to the boosted level Vcc+.alpha. higher than the power supply voltage Vcc in order to avoid the malfunction thereof.
When Vcc=5V, and Vth=1.0V, the value of .alpha. may sufficiently be 1.5 through 2.5V.
Furthermore, the control signal SA of the bit line connecting switch BSA for connecting the operating sense amplifier band (the sense amplifier band 2a in the case of the example shown in FIGS. 1 and 9) with the memory cell block (1a) is once lowered to the power supply voltage level during the operation of the sense amplifiers as shown in FIG. 9(g), to make the sense amplifiers more sensitive by temporarily increasing the on-resistance of the switch BSA and connection resistance between a bit line and a sense amplifier. In other words, a bit line is weakly connected to an associated sense amplifier to enhance the sensing speed.
However, in the above-described arrangement of the control signals, the following problems arise. Namely, when the control signal is set to the power supply voltage Vcc as shown in FIG. 9 (f), while a read voltage from a memory cell is boosted to the power supply voltage Vcc level by a sense amplifier, the power supply voltage Vcc level is transmitted to a bit line pair through an insulated gate type field effect transistor of the switch BS, so that a voltage on the bit line is reduced by a threshold voltage of the transistor included in the switch BS. Accordingly, in the rewriting of data to a selected memory cell, a voltage of Vcc-Vth level lower than the power supply voltage Vcc is written, so that the amount of electric signal charges of the of the "H" level is reduced, whereby a sufficient potential difference between the bit lines can not be produced in reading the signals of the "H" level.
As shown in FIG. 9 (g), when the control signals SA-SD are boosted to a level higher than the power supply voltage Vcc to set the transistors T10 and T11 or T15 and T16 of the switch BSA or BSB to a more highly conductive state wherein no signal loss therethrough occurs, while there occurs no such loss of a signal voltage, it is necessary to maintain the boosted level for a long time period (the time period varies depending on refreshing standard of the memory device. For example, in the case of 1 Mbit DRAM, 8 ms., while in the case of a 4 Mbit DRAM, 16 ms.) during a stand-by state or the like. In such a case, although a circuit for maintaining the control signals SA-SD at the boosted level is provided, leak currents in the signal lines transmitting the control signals SA-SD exceed holding capability of such level holding circuit, so that the potential levels of the control signals SA-SD fall, and therefore the performance which the boosted level should implement can not be obtained, resulting in deterioration in the characteristics of the semiconductor memory device or reduction in production yield.